1. Field
This disclosure relates to microphones for converting acoustic waves to electrical signals, and specifically to high performance microphone systems using electret microphones.
2. Description of the Related Art
An electrostatic microphone, also commonly called a condenser microphone, contains a fixed plate and a flexible diaphragm that collectively form a parallel plate capacitor. The diaphragm moves in response to incident acoustic waves, thus modulating the capacitance of the parallel plate capacitor. A polarizing voltage must be applied via a high value load resistor to charge or polarize the parallel plate capacitor. Variations in the capacitance in response to incident acoustic waves may then be sensed as modulation of the voltage across the capacitor.
An electret microphone is a variation of an electrostatic microphone in which at least one of the fixed plate and the diaphragm include a permanently charged dielectric layer. The presence of the permanent charge obviates the need for a polarizing voltage source to charge the parallel plate capacitor. Electret microphones are used in many applications, from high-quality sound recording to built-in microphones in consumer electronic devices. Nearly all cell-phones, computers, and headsets incorporate electret microphones.
Electret microphones are commonly produced in the form of a “capsule” containing the parallel-plate capacitor microphone and a circuit or preamplifier to transform the high impedance of the parallel-plate capacitor microphone to a lower impedance value. As shown in FIG. 1A, an electret microphone capsule 105 may include an electret microphone EM and a field-effect transistor (FET) Q1 having gate (G), source (S), and drain (D) contacts. A high value (for example, greater than 1 Gigohm) resistor R1 between the gate and drain contacts may be provided or intrinsic to the FET Q1. Although not shown in FIG. 1A, the FET Q1 will have intrinsic parasitic capacitances between the gate, drain, and source contacts and intrinsic parasitic resistances at each of the gate, drain, and source contacts. The values of the parasitic capacitances and resistances may depend, to some extent, on the voltages imposed between the contacts of the FET Q1.
The drain of the FET Q1 may be electrically connected to a first terminal T1 of the electret microphone capsule 105. The source of the FET Q1 may be electrically connected to a second terminal T2 of the electret microphone capsule 105.
The electret microphone EM may include a diaphragm 101 and a fixed plate 102. One side of the electret microphone EM (either the diaphragm 101 or the fixed plate 102) may be electrically connected to the gate of the FET Q1. In the exemplary electret microphone capsule 105 shown in FIG. 1A, the fixed plate 102 of the electret microphone EM is connected to the gate of the FET Q1. In “two-terminal” electret capsules, the second side of the electret microphone EM may be electrically connected to the source of the FET Q1 and thus the second terminal T2. In “three-terminal” electret capsules, as shown in FIG. 1A, the second side of the electret microphone EM may be electrically connected to a third terminal T3 of the electret microphone capsule 105. The third terminal T3 may be connected to a bias voltage Vbias external to the electret microphone capsule 105. The value of the bias voltage Vbias may determine, at least in part, the performance of the electret microphone EM.
Terminals T1, T2, and T3 (if present) may also be referred to as the source terminal, the drain terminal, and the bias terminal, respectively of the electret microphone capsule 105. Terminals T1, T2, and T3 may be configured to make electrical contact with corresponding terminals external to the electret microphone capsule 105. For example, terminals T1, T2, and T3 may be pins for insertion into a connector or solder pads to be reflow soldered to a circuit board external to the electret microphone capsule 105. Terminals T1, T2, and T3 may be solderless pads to electrically contact spring wipers or other structures external to the electret microphone capsule 105. Terminals T1, T2, and T3 may be some other structures or devices for making electrical contact to corresponding terminals external to the electret microphone capsule 105.
The drain and source of the FET Q1 may be separately connected via terminals T1 and T2, respectively, to components external to the electret microphone capsule 105. In the example of FIG. 1A, the FET Q1 is used as an inverting preamplifier. The source of FET Q1 is electrically connected to ground via terminal T2, and a voltage VDS is applied to the drain of FET Q1 through a load resistor RL, and terminal T1. A signal voltage applied to the gate of the FET Q1 by the electret microphone EM will be amplified by the FET Q1. The amplified signal may be output from the electret microphone capsule 105 at terminal T1. In this configuration, the voltage between the source and gate of FET Q1 will vary in accordance with the amplified output signal. Variations of the voltage between the source and drain of FET Q1 will cause corresponding changes in the parasitic capacitances within FET Q1, which may contribute to distortion of the amplified signal. Additionally, the apparent input capacitance of the FET Q1 will be increased due to Miller-effect multiplication of the parasitic gate-source capacitance of the FET Q1. The high apparent input capacitance is effectively in parallel with the capacitance of the electret microphone EM, and thus may reduce the audio signal level output from the electret microphone EM. Additionally, since parasitic gate-source capacitance of the FET Q1 may vary nonlinearly with voltage, the Miller-effect multiplication of this capacitance may cause distortion of the audio signal.
In the example of FIG. 1B, the FET Q1 is used as source follower. The source of FET Q1 is electrically connected to ground via terminal T2 and a load resistor RL, and a voltage VDS is applied to the drain of FET Q1 via terminal T1. A signal voltage applied to the gate of the FET Q1 by the electret microphone EM will be output from terminal T2 without amplification. In this configuration, the voltage between the source and gate of FET Q1 will vary in accordance with the amplified output signal. Variations of the voltage between the source and drain of FET Q1 will cause corresponding changes in the parasitic capacitances within FET Q1, which may contribute to distortion of the amplified signal. However, the apparent input capacitance of the FET Q1 will be lower than that of the configuration of FIG. 1A.
Throughout this description, elements appearing in figures are assigned three-digit reference designators, where the most significant digit is the figure number where the element first appears, and the two least significant digits are specific to the element. In electrical schematic diagrams, circuit components may be assigned conventional labels. The same labels (for example “R1”) may serve both to identify the component within a schematic diagram and to represent the value of the component in formulas. An element that is not described in conjunction with a figure may be presumed to have the same characteristics and function as a previously-described element having the same label or reference designator.